1. Field of the Invention
This invention generally relates to methods and systems for determining a position of output generated by an inspection subsystem in design data space.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
An integrated circuit (IC) design may be developed using a method or system such as electronic design automation (EDA), computer aided design (CAD), and other IC design software. Such methods and systems may be used to generate the circuit pattern database from the IC design. The circuit pattern database includes data representing a plurality of layouts for various layers of the IC. Data in the circuit pattern database may be used to determine layouts for a plurality of reticles. A layout of a reticle generally includes a plurality of polygons that define features in a pattern on the reticle. Each reticle is used to fabricate one of the various layers of the IC. The layers of the IC may include, for example, a junction pattern in a semiconductor substrate, a gate dielectric pattern, a gate electrode pattern, a contact pattern in an interlevel dielectric, and an interconnect pattern on a metallization layer.
The term “design data” as used herein generally refers to the physical design (layout) of an IC and data derived from the physical design through complex simulation or simple geometric and Boolean operations.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield in the manufacturing process and thus higher profits. Inspection has always been an important part of fabricating semiconductor devices such as ICs. However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail.
As design rules shrink, however, semiconductor manufacturing processes may be operating closer to the limitations on the performance capability of the processes. In addition, smaller defects can have an impact on the electrical parameters of the device as the design rules shrink, which drives more sensitive inspections. Therefore, as design rules shrink, the population of potentially yield relevant defects detected by inspection grows dramatically, and the population of nuisance defects detected by inspection also increases dramatically. Therefore, more and more defects may be detected on the wafers, and correcting the processes to eliminate of the defects may be difficult and expensive.
Recently, inspection systems and methods are increasingly being designed to focus on the relationship between defect and design since it is the impact on the design for a wafer that will determine whether and how much a defect matters. For example, some methods have been developed for aligning inspection and design coordinates. One such method depends on the accuracy of the inspection system coordinate registration to design. Another such method involves conducting post-processing alignment on the inspection image patch and associated design clip.
There are, however, a number of disadvantages to many of the existing inspection systems and methods. For example, when the methods depend on the accuracy of the inspection system coordinate registration to design, the methods do not necessarily provide the alignment accuracy that is needed. In addition, post-processing alignment of the inspection image patch and associated design clip is dependent on having sufficient information in the inspection patch and design clip. Often, it is the case that this criteria is not met, and the defects concerned cannot be used in the rest of the analysis or worse yet bad data is propagated through the remainder of the analysis thereby reducing the accuracy of the outcome.
Accordingly, it would be advantageous to develop systems and/or methods for determining a position of output generated by an inspection subsystem in design data space that do not have one or more of the disadvantages described above.